In many digital logic applications, it is desirable to monitor a collection of digital signals and initiate an action or perform a particular function whenever a pattern appears which falls within a predetermined range of values. To serve this purpose, an apparatus must be provided which can test any given pattern in the monitored signals to determine if the pattern lies within the preselected range of values. Ideally, such an apparatus would provide fast operation, use of a minimum of parts, and be capable of checking a pattern against a number of ranges.
One prior approach in constructing a range testing apparatus is exemplified by U.S. Pat. No. 4,100,532, entitled Digital Pattern Triggering Circuit and issued to William A. Farnbach. This prior art scheme uses q-many memories to check an n-bit input pattern against a lower bound. Each memory has 2.sup.n/q .times.2 locations. One output bit indicates a partial greater than condition, while another represents a partial equality condition. The outputs of the memories are fed to a series of at least q-many gates, which determines if the tested pattern is greater in numerical value than a chosen lower bound. An analogous structure, using q-many more memories and gates, is used to check the pattern against an upper bound. The outputs of the two structures are fed to yet another gate which indicates whether the tested pattern is within the range defined by the upper and lower bounds. Thus, by using 2q memories and 2q+1 gates, an input value may be checked against a single range of consecutive numerical values.
One disadvantage of this approach is that only a single set of numerical values, delimited by an upper and lower bound, may be used as the predetermined range at any one time. While this may be sufficient for some applications, it is often desirable to check an input value against several ranges at once to enable different actions to be performed, depending on which range or combination of ranges contains the tested value. Since the Farnbach scheme can test against only one range at a time, several parallel structures, each using 2q memories and 2q+1 gates, must be used to test a pattern against multiple ranges.
Accordingly, it is an object of the present invention to provide a method and apparatus to check an input parameter against a range with a minimum of time and memory.
A further object of the invention is to accommodate an increase in the number of ranges without decreasing the speed of operation and with a minimal increase in the amount of memory required.
Another object of the invention is to accommodate arbitrary ranges defined with values having more bits than available memories have address bits.
Still another object of the invention is to allow a mix of arbitrary and disjoint ranges to be recognized, wherein for each arbitrary range not defined several disjoint ranges are definable in its place.